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Posted at 7/6/2018 09:57:26
2#
Hello elect123, you can have a try as belowed:
/* HS hsfreqrange & lane 0 settle bypass */
mipi_dphy0_wr_reg(isp_cfg, 0x44, hsfreqrange);
mipi_dphy0_wr_reg(isp_cfg, 0x54, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x84, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x94, 0);
mipi_dphy0_wr_reg(isp_cfg, 0x75, 0x04);
mipi_dphy0_rd_reg(isp_cfg, 0x75);
/* Make N and M factors configuration effective */
mipi_dphy1_wr_reg(isp_cfg, 0x19, 0x30);
/* PLL Input Divider Ratio (N) programmed */
mipi_dphy1_wr_reg(isp_cfg, 0x17, 0x02);
/* PLL Loop Divider Ratio (M) programmed */
mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x03); //lsb
mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x83); //msb
/*
* VCO Control (vcorange and vcocap) programmed
* VCO range= 3'b100
* Vcocap = 2'b00
*/
mipi_dphy1_wr_reg(isp_cfg, 0x10, 0xA1);
/* PLL Control (icpctrl) programmed */
mipi_dphy1_wr_reg(isp_cfg, 0x11, 0x06);
/* PLL Control (lpfctrl) programmed and allow 0x11 to be effective */
mipi_dphy1_wr_reg(isp_cfg, 0x12, (0xC0|0x4));
good luck for you! |
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