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How to setting mipi pll setting on RK3399

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Posted at 6/15/2018 08:24:14     
Last edited by elect123 In 6/20/2018 09:28 Editor

The current situation works normally under 800Mbps.

I want to know PLL Programming
REFCLK = 27 MHz case (Over 800Mbps Under 1Gbps)

I found 419 page in Rockchip RK3399TRM V1.3 Part2.pdf file
But Cases are under 800 Mbps

And I changed mipi_dphy_cfg() in cif_isp10_rk3399.c


If set to over 800Mbps , an interrupt error occurs.
Under 800Mbps not generated.
[   12.884399] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
[   12.884985] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.885532] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
[   12.886120] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x500003
[   12.886703] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.887254] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300003
[   12.887835] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.888387] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x500003
[   12.888968] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
Thanks & regard
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Posted at 6/25/2018 16:41:01     
Last edited by elect123 In 6/25/2018 16:43 Editor

I waiting your response


Is it possible to set 800Mbps per mipi line?




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Posted at 7/1/2018 21:51:26     
if you want to do PLL Programming @REFCLK=27HMZ(Over 800Mbps Under 1Gbps),please to do the sequence as belowed:

1、hsfreqrange[5:0] = desired value, the value you can find in  Frequency Ranges table in RK3399TRM V1.3;
2、Make N and M factors configuration effective:test code 0x19 = 0x30;
3、PLL Input Divider Ratio (N) programmed: test code 0x17 = desired value,
     the value range is :800-899(Mbps)= 2;900-999(Mbps)= 1;
4、PLL Loop Divider Ratio (M) programmed:test code 0x18 = desired value,lsb first,the msb,
     the value range is(dec) :800-849 Mbps = 93,850-899 Mbps = 99; 900 -949 Mbps = 69; 950-999 Mbps = 73;
5、VCO Control (vcorange and vcocap) programmed: test code 0x10 = desired value;
      VCO range is :
      vcorange[2:0]   800-899Mbps =100, 900-999Mbps = 101
      vcocap[1:0] always be set as 0x0;
6、PLL Control (icpctrl) programmed: test code 0x11= desired value
      icpctrl[3:0] : 800-899 Mbps = 0110 , 900-999 Mbps = 1011
7、PLL Control (lpfctrl) programmed and allow 0x11 to be effective:test code  0x12 = 0xc | desired value,
       value =lpfctrl[5:0] :800-899 Mbps = 000100,900-999 Mbps = 010000

      best of luck !
      




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Posted at 7/2/2018 13:31:02     
Last edited by elect123 In 7/4/2018 18:25 Editor

Dear tannyhjl

I have tried the above settings but I still get an interrupt error
Please confirm that the modified code is correct.
My target setting is 891Mhz
I modified file and function
mipi_dphy_cfg() in cif_isp10_rk3399.c
                /* set clock lane */
                mipi_dphy1_wr_reg(isp_cfg, 0x34, 0x00);
                mipi_dphy1_wr_reg(isp_cfg, 0x44, hsfreqrange);//0x39<<1
/////////////////////This is your setting. I modified /////////////////////////////////////////
               mipi_dphy1_wr_reg(isp_cfg, 0x19, 0x30);      
               mipi_dphy1_wr_reg(isp_cfg, 0x17, 0x01);      
               mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x02);      
               mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x83);      
               mipi_dphy1_wr_reg(isp_cfg, 0x10, 0x80 | 0x01 | (0x4 << 3));      
               mipi_dphy1_wr_reg(isp_cfg, 0x11, 0x06);      
               mipi_dphy1_wr_reg(isp_cfg, 0x12, (0xC0|0x4));
/////////////////////////////////////////////////////////////////////////////////////////////////
                mipi_dphy1_wr_reg(isp_cfg, 0x54, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x84, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x94, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x75, 0x04);

                mipi_dphy1_rd_reg(isp_cfg, 0x0);

Thanks & regard !
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Posted at 7/6/2018 09:57:26     
Hello elect123, you can have a  try as belowed:

                /* HS hsfreqrange & lane 0  settle bypass */
                mipi_dphy0_wr_reg(isp_cfg, 0x44, hsfreqrange);
                mipi_dphy0_wr_reg(isp_cfg, 0x54, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x84, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x94, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x75, 0x04);
                mipi_dphy0_rd_reg(isp_cfg, 0x75);
               
                /* Make N and M factors configuration effective */
                mipi_dphy1_wr_reg(isp_cfg, 0x19, 0x30);
               
                /* PLL Input Divider Ratio (N) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x17, 0x02);
               
                /* PLL Loop Divider Ratio (M) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x03); //lsb  
        mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x83); //msb
               
                /*
                 * VCO Control (vcorange and vcocap) programmed
                 * VCO range= 3'b100
                 * Vcocap = 2'b00
                 */
                mipi_dphy1_wr_reg(isp_cfg, 0x10, 0xA1);
               
                /* PLL Control (icpctrl) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x11, 0x06);
               
                /* PLL Control (lpfctrl) programmed and allow 0x11 to be effective */
                mipi_dphy1_wr_reg(isp_cfg, 0x12, (0xC0|0x4));

       good luck for you!
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Posted at 7/9/2018 09:11:59     
Dear tannyhjl
I have tried the above settings but I still get an interrupt error
Do you have any other check points?
Thanks & regard !
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