Title: Possible bug in schematic or PCB with SD/MMC slot? [Print This Page] Author: Astralix Time: 1/7/2015 00:21 Title: Possible bug in schematic or PCB with SD/MMC slot? Hi!
While discussing mainline kernel implementation of SD/MMC for firefly I checked schematics and found, that the termination resistors of socket J4 are connected to VCC_SD. But VCC_SD is switched 3V3 derived from VCC_IO via MOS FET Q22.
To be UHS compliant, the termination must be connected to VCCIO_SD, as the data and command lines are switched to 1V8 by this line in UHS mode while staying at 3V3 in standard mode. The termination resistors need to be switched to 1V8 too in UHS mode.
Is it only a bug in the schematics or is there a little bug in the PCB design?
Furthermore the resistors for termination may be of the wrong value.
According JEDEC eMMC specification 4.51 (JESD84-B451.pdf, pages 220ff), termination is 10k to 100k (see table 160).
In the comments 1) is stated that 1V8 is good up to 50k. I am not sure if the lowest allowed value (10k) is the best choice to get high speed signals in a good shape.
Actually I do not have an active probe for my digital oscylloscope, so I cannot check if there is a better value.
kind regards
Astralix
Author: busybee Time: 1/8/2015 15:23
Hi Astralix. We have not tested UHS card yet.
Have you met with any problem?
Author: Anonymous Time: 9/24/2016 13:52
Tip: the author has been banned or deleted automatically shield Author: Anonymous Time: 9/25/2016 11:35
Tip: the author has been banned or deleted automatically shield Author: Anonymous Time: 10/22/2016 16:25
Tip: the author has been banned or deleted automatically shield Author: jpboard Time: 6/21/2018 18:31
wow 29 pages of spam what a waste of time and space after one good postAuthor: c818919 Time: 10/21/2019 08:01
That concept seems like being hd audio but not being hi res audio badged.
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