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Title: Enable The I2S MCLK [Print This Page]
Author: sweckhoff Time: 10/8/2015 13:55
Title: Enable The I2S MCLK
Hello,
Has anyone figured out how to enable this?
I would like to keep it on all the time.
The bit clock and frame clocks are working as expected. Now I just need to get MCLK for my application.
Thanks!
Author: sweckhoff Time: 10/10/2015 00:20
Last edited by sweckhoff In 10/19/2015 06:03 Editor
I am seeing an external MCLK during probe and then it turns off. I would like to have a constant MCLK from probe on. Is this possible with the current drivers?
Author: sweckhoff Time: 10/23/2015 10:52
It seems like the Rockchip BSP has many errors. Here is what I am seeing in the DT and the I2S driver
Device Tree (NOTE: The pinctrl has been modified because they wouldn't compile when uncommented. This was just another bug.)
473 i2s0: i2s0@10220000 {
474 compatible = "rockchip-i2s";
475 reg = <0x10220000 0x1000>;
476 i2s-id = <0>;
477 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
478 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
479 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
480 dmas = <&pdma 0>, <&pdma 1>;
481 //#dma-cells = <2>;
482 dma-names = "tx", "rx";
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2s0_mclk_mux0 &i2s0_sclk_mux0 &i2s0_lrckrx_mux0 &i2s0_lrcktx_mux0 &i2s0_sdi_mux0 &i2s0_sdo_mux0>;
485 //pinctrl-0 = <&i2s0_sclk_mux0 &i2s0_lrckrx_mux0 &i2s0_lrcktx_mux0 &i2s0_sdi_mux0 &i2s0_sdo_mux0>;
486 status = "okay";
487 };
488
489 i2s1: i2s1@10200000 {
490 compatible = "rockchip-i2s";
491 reg = <0x10200000 0x1000>;
492 i2s-id = <1>;
493 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
494 clock-names = "i2s_clk", "i2s_hclk";
495 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
496 dmas = <&pdma 14>, <&pdma 15>;
497 //#dma-cells = <2>;
498 dma-names = "tx", "rx";
499 };
From the I2S Driver
452 struct snd_soc_dai_driver rockchip_i2s_dai[] = {
453 {
454 .name = "rockchip-i2s.0",
455 .id = 0,
456 .playback = {
457 .channels_min = 2,
458 .channels_max = 8,
459 .rates = ROCKCHIP_I2S_STEREO_RATES,
460 .formats = ROCKCHIP_I2S_FORMATS,
461 },
462 .capture = {
463 .channels_min = 2,
464 .channels_max = 2,
465 .rates = ROCKCHIP_I2S_STEREO_RATES,
466 .formats = ROCKCHIP_I2S_FORMATS,
467 },
468 .ops = &rockchip_i2s_dai_ops,
469 .symmetric_rates = 1,
470 },
471 {
472 .name = "rockchip-i2s.1",
473 .id = 1,
474 .playback = {
475 .channels_min = 2,
476 .channels_max = 2,
477 .rates = ROCKCHIP_I2S_STEREO_RATES,
478 .formats = ROCKCHIP_I2S_FORMATS,
479 },
480 .capture = {
481 .channels_min = 2,
482 .channels_max = 2,
483 .rates = ROCKCHIP_I2S_STEREO_RATES,
484 .formats = ROCKCHIP_I2S_FORMATS,
485 },
486 .ops = &rockchip_i2s_dai_ops,
487 .symmetric_rates = 1,
488 },
489 };
The number of channels on each I2S interface are swapped! Does anyone know what's what with this?
Author: jonsmirl Time: 10/27/2015 04:56
The naming is incorrect in the device tree. Look at the reg = <>. The one with the higher address is named I2S0. It just appears to be named wrong. The eight channel I2S is what makes HDMI audio, 8-channel I2S is not accessible on the external pins.
The device tree names can be anything, they are just strings. So this is confusing to a human but the computer doesn't care. The computer does not understand this "i2s1: i2s1@10200000" except as a collection of unique strings. You could name it "blue:rabbit@hat" and the DTC won't care.
Author: jonsmirl Time: 10/27/2015 05:06
A likely cause for MCLK turning off is that there is default code somewhere turning unused pins into input GPIOs to save power. I have not looked, but you probably need to write a clock driver for the MCLK pin and support it in PINCTRL. In the DTS IS1 would then depend on this MCLK. Which would trigger the clock driver to turn it on. Implementing the clock driver marks the pin as in-use and will block the default GPIO behavior. This is not a lot of code, maybe 30-40 lines.
Author: jonsmirl Time: 10/27/2015 05:07
The I2S section is also missing support for enabling an external I2S clock.
Author: sweckhoff Time: 10/31/2015 10:36
Thanks a lot for the help. I will look into this and let you know if it helps.
Overall this is a frustrating platform to work with.
Author: jonsmirl Time: 11/5/2015 08:09
This is way better than most other Chinese SOCs.
Allwinner only has support because volunteers are doing it, Allwinner pays them nothing.
Author: Zuy Time: 1/12/2016 01:50
Hi, have you finally solved your problem?
Could you please share kernel sources?
I also have to connect external audio codec to RK3128 and having some difficulties.
Author: woody.lee Time: 2/4/2016 13:08
Hi sweckhoff,
Have you finally solved your problem?
Could you please share kernel sources?
I also have to connect external audio codec(SSM2603) to RK3128 and having "lots" difficulties.
Author: zhansb Time: 2/16/2016 17:01
[size=13.63636302948px]try to add the following codec to enable I2s0 clk in rk30_i2s.c :
i2s->clk_i2s_2ch_out = clk_get(&pdev->dev, "clk_i2s_2ch_out");
if (IS_ERR(i2s->clk_i2s_2ch_out)) {
dev_err(&pdev->dev, "Can't retrieve clk_i2s_2ch_out\n");
ret = PTR_ERR(i2s->clk_i2s_2ch_out);
goto err;
}
clk_prepare_enable(i2s->clk_i2s_2ch_out);
Author: Birender Time: 2/27/2017 04:51
Is 8 channel i2S accessible on external pins in RK3128 like RK3066 and RK3288 ?
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