Possible bug in schematic or PCB with SD/MMC slot?

Astralix

Hi!

While discussing mainline kernel implementation of SD/MMC for firefly I checked schematics and found, that the termination resistors of socket J4 are connected to VCC_SD. But VCC_SD is switched 3V3 derived from VCC_IO via MOS FET Q22.

To be UHS compliant, the termination must be connected to VCCIO_SD, as the data and command lines are switched to 1V8 by this line in UHS mode while staying at 3V3 in standard mode. The termination resistors need to be switched to 1V8 too in UHS mode.

Is it only a bug in the schematics or is there a little bug in the PCB design?

Furthermore the resistors for termination may be of the wrong value.
According JEDEC eMMC specification 4.51 (JESD84-B451.pdf, pages 220ff), termination is 10k to 100k (see table 160).
In the comments 1) is stated that 1V8 is good up to 50k. I am not sure if the lowest allowed value (10k) is the best choice to get high speed signals in a good shape.
Actually I do not have an active probe for my digital oscylloscope, so I cannot check if there is a better value.

kind regards
Astralix