Title: RK3288 DDR3 Write Leveling [Print This Page] Author: prkarls Time: 7/16/2019 04:30 Title: RK3288 DDR3 Write Leveling From what I can tell by reading the TRM, the RK3288 supports DDR3 write leveling.
For some reason I can't seem to get the write leveling routine to run to compensate for the individual byte lane skews. According to the DDR_PCTL_DFITRSTAT0 register, the PHY is configured for PHY Independent mode. In PHY Independent mode, the PHY is responsible for executing data eye training, gate training or write leveling independent of the MC. In this mode, the associated training interface is not used other than the mode signal to the MC. The MC should be capable of generating the required MRS commands to enter or exit the test modes of the memory devices. These operations are not automatically generated. All training sequences, regardless of mode, are expected to be executed after memory initialization. For PHY Independent mode, the update interface may be used to suspend memory commands while the training sequences are executed.
I am able to configure the DRAMs for write leveling using the appropriate MRS commands, but it doesn't seem to trigger anything. Does anyone know what I need to do to trigger a write leveling routine?
Thanks!Author: penguin Time: 7/25/2019 09:17
AFAIK, Kever from RK has answered your question in the U-Boot mail list that RK3288 does not support DDR3 Write Leveling.
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