Firefly Open Source Community

   Login   |   Register   |
New_Topic
Print Previous Topic Next Topic

[Linux] How to setting mipi pll setting on RK3399

28

Credits

0

Prestige

0

Contribution

new registration

Rank: 1

Credits
28
Posted at 7/1/2018 21:51:26      1#
if you want to do PLL Programming @REFCLK=27HMZ(Over 800Mbps Under 1Gbps),please to do the sequence as belowed:

1、hsfreqrange[5:0] = desired value, the value you can find in  Frequency Ranges table in RK3399TRM V1.3;
2、Make N and M factors configuration effective:test code 0x19 = 0x30;
3、PLL Input Divider Ratio (N) programmed: test code 0x17 = desired value,
     the value range is :800-899(Mbps)= 2;900-999(Mbps)= 1;
4、PLL Loop Divider Ratio (M) programmed:test code 0x18 = desired value,lsb first,the msb,
     the value range is(dec) :800-849 Mbps = 93,850-899 Mbps = 99; 900 -949 Mbps = 69; 950-999 Mbps = 73;
5、VCO Control (vcorange and vcocap) programmed: test code 0x10 = desired value;
      VCO range is :
      vcorange[2:0]   800-899Mbps =100, 900-999Mbps = 101
      vcocap[1:0] always be set as 0x0;
6、PLL Control (icpctrl) programmed: test code 0x11= desired value
      icpctrl[3:0] : 800-899 Mbps = 0110 , 900-999 Mbps = 1011
7、PLL Control (lpfctrl) programmed and allow 0x11 to be effective:test code  0x12 = 0xc | desired value,
       value =lpfctrl[5:0] :800-899 Mbps = 000100,900-999 Mbps = 010000

      best of luck !
      




Reply

Use props Report

28

Credits

0

Prestige

0

Contribution

new registration

Rank: 1

Credits
28
Posted at 7/6/2018 09:57:26      2#
Hello elect123, you can have a  try as belowed:

                /* HS hsfreqrange & lane 0  settle bypass */
                mipi_dphy0_wr_reg(isp_cfg, 0x44, hsfreqrange);
                mipi_dphy0_wr_reg(isp_cfg, 0x54, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x84, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x94, 0);
                mipi_dphy0_wr_reg(isp_cfg, 0x75, 0x04);
                mipi_dphy0_rd_reg(isp_cfg, 0x75);
               
                /* Make N and M factors configuration effective */
                mipi_dphy1_wr_reg(isp_cfg, 0x19, 0x30);
               
                /* PLL Input Divider Ratio (N) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x17, 0x02);
               
                /* PLL Loop Divider Ratio (M) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x03); //lsb  
        mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x83); //msb
               
                /*
                 * VCO Control (vcorange and vcocap) programmed
                 * VCO range= 3'b100
                 * Vcocap = 2'b00
                 */
                mipi_dphy1_wr_reg(isp_cfg, 0x10, 0xA1);
               
                /* PLL Control (icpctrl) programmed */
                mipi_dphy1_wr_reg(isp_cfg, 0x11, 0x06);
               
                /* PLL Control (lpfctrl) programmed and allow 0x11 to be effective */
                mipi_dphy1_wr_reg(isp_cfg, 0x12, (0xC0|0x4));

       good luck for you!
Reply

Use props Report

You need to log in before you can reply Login | Register

This forum Credits Rules

Quick Reply Back to top Back to list