How to setting mipi pll setting on RK3399

elect123

The current situation works normally under 800Mbps.

I want to know PLL Programming
REFCLK = 27 MHz case (Over 800Mbps Under 1Gbps)

I found 419 page in Rockchip RK3399TRM V1.3 Part2.pdf file
But Cases are under 800 Mbps

And I changed mipi_dphy_cfg() in cif_isp10_rk3399.c


If set to over 800Mbps , an interrupt error occurs.
Under 800Mbps not generated.
[   12.884399] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
[   12.884985] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.885532] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
[   12.886120] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x500003
[   12.886703] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.887254] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300003
[   12.887835] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x3
[   12.888387] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x500003
[   12.888968] cif_isp10_mipi_isr(6550) ERR: mipi_mis icr err: 0x300000
Thanks & regard

elect123

I waiting your response


Is it possible to set 800Mbps per mipi line?

elect123

Dear tannyhjl

I have tried the above settings but I still get an interrupt error
Please confirm that the modified code is correct.
My target setting is 891Mhz
I modified file and function
mipi_dphy_cfg() in cif_isp10_rk3399.c
                /* set clock lane */
                mipi_dphy1_wr_reg(isp_cfg, 0x34, 0x00);
                mipi_dphy1_wr_reg(isp_cfg, 0x44, hsfreqrange);//0x39<<1
/////////////////////This is your setting. I modified /////////////////////////////////////////
               mipi_dphy1_wr_reg(isp_cfg, 0x19, 0x30);      
               mipi_dphy1_wr_reg(isp_cfg, 0x17, 0x01);      
               mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x02);      
               mipi_dphy1_wr_reg(isp_cfg, 0x18, 0x83);      
               mipi_dphy1_wr_reg(isp_cfg, 0x10, 0x80 | 0x01 | (0x4 << 3));      
               mipi_dphy1_wr_reg(isp_cfg, 0x11, 0x06);      
               mipi_dphy1_wr_reg(isp_cfg, 0x12, (0xC0|0x4));
/////////////////////////////////////////////////////////////////////////////////////////////////
                mipi_dphy1_wr_reg(isp_cfg, 0x54, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x84, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x94, 0);
                mipi_dphy1_wr_reg(isp_cfg, 0x75, 0x04);

                mipi_dphy1_rd_reg(isp_cfg, 0x0);

Thanks & regard !

elect123

Dear tannyhjl
I have tried the above settings but I still get an interrupt error
Do you have any other check points?
Thanks & regard !